CXMT reports progress on denser DRAM cell design

what happened

ChangXin Memory Technologies (CXMT) has advanced work on a redesigned memory cell intended to raise DRAM density and efficiency, the South China Morning Post reported. CXMT president Cao Kanyu discussed the development at an industry gathering in Shanghai over the weekend. A company statement said a server-memory product using the technology is scheduled for release by the end of 2026.

The “4F square” layout is intended to pack more cells onto a chip. Each cell covers four square F, with F denoting the minimum semiconductor line width; conventional commercial DRAM generally uses a 6F square cell. CXMT said its approach is built around a proprietary Vertical Surrounding Gate transistor. Its upright gate structure is designed to limit current leakage, reduce cell dimensions and raise storage density.

Moving to 4F square requires replacing horizontal transistor channels with vertical ones. CXMT said its existing production methods could not simply be carried over, forcing a redesign of critical processes to balance performance with power use. Competitors are working on the same concept: SK Hynix published a 4F square roadmap in 2025, while Samsung reportedly aims to start mass-producing sub-10-nanometer DRAM with the design by 2028, according to South Korean outlet The Elec.

why it matters

The development highlights intensifying competition in DRAM technology, with manufacturers seeking higher density while managing power consumption and process complexity.

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